Low Jitter And Skew 10 To 140 Mhz Zero Delay Buffer (zdb)

The SL2309 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to nine (9) Clock outputs from one (1) reference input Clock for high speed Clock Distribution applications. The product has an on-chip PLL which locks to the input Clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL2309 has two (2) Clock Driver banks each with four (4) Clock outputs. These outputs are controlled by two (2) select input pins S1 and S2. When only four (4) outputs are needed, four (4) bank-B output Clock Buffers CAN be tri- stated to reduce power dissipation and jitter. The select inputs CAN also be used to tri-state both banks A and B or drive them directly from the input bypassing the PLL and making the product behave like a Non-Zero Delay Buffer (NZDB). The high-drive (-1H) version operates up to 140MHz and low drive (-1) version operates up to 100MHz at 3.3V. By Unkown
SL2309 's PackagesSL2309 's pdf datasheet
SL2309ZC-1
SL2309ZC-1T
SL2309ZC-1H
SL2309ZC-1HT
SL2309ZI-1
SL2309ZI-1T
SL2309ZI-1H
SL2309ZI-1HT




SL2309 Pinout, Pinouts
SL2309 pinout,Pin out
This is one package pinout of SL2309,If you need more pinouts please download SL2309's pdf datasheet.

SL2309 Application circuits
SL2309 circuits
This is one application circuit of SL2309,If you need more circuits,please download SL2309's pdf datasheet.


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SL2309 Pb-Free SL2309 Cross Reference SL2309 Schematic SL2309 Distributor
SL2309 Application Notes SL2309 RoHS SL2309 Circuits SL2309 footprint
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