DDR2 Configurable Registered Buffer With Parity

The SLGSSTUA32866 is a configurable registered Buffer with parity designed for 1.7V to 1.9V VDD oper- ating range. All Clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control and reset inputs are LVCMOS. All data outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18 specifications. The error (QERR) output is 1.8V open-drain driver. By Silego Semiconductor
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