DDR2 Configurable Registered Buffer With ParityThe SLGSSTUB32865 is a registered Buffer with parity designed for 1.7V to 1.9V VDD operating range.
All Clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control and reset
inputs are LVCMOS. All data outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2
DIMM load, and meet SSTL_18 specifications. The error (PTYERR) output is 1.8V open-drain driver. By Silego Semiconductor
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| SLGSSTUB32865 Pb-Free | SLGSSTUB32865 Cross Reference | SLGSSTUB32865 Schematic | SLGSSTUB32865 Distributor |
| SLGSSTUB32865 Application Notes | SLGSSTUB32865 RoHS | SLGSSTUB32865 Circuits | SLGSSTUB32865 footprint |
