1.8V PLL Clock Driver For DDR2The SLGUA877 is a PLL based zero delay Buffer designed for 1.7V to 1.9V VDD operating range. The dif-
ferential Clock input pair (CLK/ CLK) is distributed to 10 differential output pairs (Y[0:9]/ Y[0:9]) and one dif-
ferential feedback pair (FBOUT/ FBOUT). All output pairs are controlled by: (CLK/ CLK) inputs, (FBIN/
FBIN) inputs, OS,OE inputs, and Analog VDD supply pin (AVDD) By Silego Semiconductor
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| SLGUA877 Pb-Free | SLGUA877 Cross Reference | SLGUA877 Schematic | SLGUA877 Distributor |
| SLGUA877 Application Notes | SLGUA877 RoHS | SLGUA877 Circuits | SLGUA877 footprint |
