1.8V PLL Clock Driver For DDR2

The SLGUA877 is a PLL based zero delay Buffer designed for 1.7V to 1.9V VDD operating range. The dif- ferential Clock input pair (CLK/ CLK) is distributed to 10 differential output pairs (Y[0:9]/ Y[0:9]) and one dif- ferential feedback pair (FBOUT/ FBOUT). All output pairs are controlled by: (CLK/ CLK) inputs, (FBIN/ FBIN) inputs, OS,OE inputs, and Analog VDD supply pin (AVDD) By Silego Semiconductor
SLGUA877 's PackagesSLGUA877 's pdf datasheet



SLGUA877 Pinout, Pinouts
SLGUA877 pinout,Pin out
This is one package pinout of SLGUA877,If you need more pinouts please download SLGUA877's pdf datasheet.

SLGUA877 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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