2.5V PLL Clock Driver For DDR 2.5V PLL Clock Driver For DDR

The SLGVF857 is a PLL based zero delay Buffer designed for 2.3V to 2.7V VDD operating range. The dif- ferential Clock input pair (CLK, CLK) is distributed to 10 differential output pairs (Y[0:9],Y[0:9]) and one dif- ferential feedback pair (FBOUT, FBOUT). All output pairs are controlled by: (CLK,CLK) inputs, (FBIN, FBIN) inputs, PWRDWN input, and Analog VDD supply pin (AVDD). By Broadcom Corp.
SLGVF857 's PackagesSLGVF857 's pdf datasheet
SLGVF857H-TR
SLGVF857L-TR
SLGVF857V-TR
SLGVF857V
SLGVF857H
SLGVF857L




SLGVF857 Pinout, Pinouts
SLGVF857 pinout,Pin out
This is one package pinout of SLGVF857,If you need more pinouts please download SLGVF857's pdf datasheet.

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