2.5V Low Power PLL Clock Driver For DDR1

The SLGVF857C-14 is a PLL based zero delay Buffer designed for 2.3V to 2.7V VDD operating range. The differential Clock input pair (CLK, CLK) is distributed to 10 differential output pairs (Y[0:9],Y[0:9]) and one differential feedback pair (FBOUT, FBOUT). All output pairs are controlled by: (CLK,CLK) inputs, (FBIN, FBIN) inputs, PWRDWN input, and Analog VDD supply pin (AVDD). By Silego Semiconductor
SLGVF857C-14 's PackagesSLGVF857C-14 's pdf datasheet
SLGVF857C-14H TSSOP
SLGVF857C-14F TSSOP
SLGVF857C-14L TVSOP
SLGVF857C-14V QFN
SLGVF857C-14H-TR TSSOP
SLGVF857C-14F-TR TSSOP
SLGVF857C-14L-TR TVSOP




SLGVF857C-14 Pinout, Pinouts
SLGVF857C-14 pinout,Pin out
This is one package pinout of SLGVF857C-14,If you need more pinouts please download SLGVF857C-14's pdf datasheet.

SLGVF857C-14 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

SLGVF857C-14 Pb-Free SLGVF857C-14 Cross Reference SLGVF857C-14 Schematic SLGVF857C-14 Distributor
SLGVF857C-14 Application Notes SLGVF857C-14 RoHS SLGVF857C-14 Circuits SLGVF857C-14 footprint