DIGITAL SIGNAL PROCESSORS

DIGITAL SIGNAL PROCESSORS SM320C6201 The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every Clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following Clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets CAN vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C6200 CPU from other VLIW architectures. By Texas Instruments