DIGITAL SIGNAL PROCESSORSDIGITAL SIGNAL PROCESSORS SM320C6201 The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight
32-bit instructions to the eight functional units during every Clock cycle. The VelociTI VLIW architecture features
controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The
first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the
previous instruction, or whether it should be executed in the following Clock as a part of the next execute packet.
Fetch packets are always 256 bits wide; however, the execute packets CAN vary in size. The variable-length
execute packets are a key memory-saving feature, distinguishing the C6200 CPU from other VLIW
architectures. By Texas Instruments
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Part | Manufacturer | Description | Datasheet | Samples | |
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SM320C6201BGLPS20 | Texas Instruments | Fixed-Point Digital Signal Processor, Military 429-CFCBGA -40 to 90 | |||
SM320C6201GJCA20EP | Texas Instruments | Enhanced Product Fixed-Point Digital Signal Processor, Military 352-FCBGA -40 to 105 |
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SM320C6201 Pb-Free | SM320C6201 Cross Reference | SM320C6201 Schematic | SM320C6201 Distributor |
SM320C6201 Application Notes | SM320C6201 RoHS | SM320C6201 Circuits | SM320C6201 footprint |