FIXED-POINT DIGITAL SIGNAL PROCESSOR

The SMJ320LC549 fixed-point, digital signal processor (DSP) (hereafter referred to as the 549) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. The processor also provides an arithmetic Logic unit (ALU) that has a high degree of parallelism, application-specific hardware Logic on-chip memory, and additional on-chip peripherals. The 549 also utilizes a highly specialized instruction set, which is the basis of its operational flexibility and speed. Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two reads and one write operation CAN be performed in a single cycle. Instructions with parallel store and application-specific instructions CAN fully utilize this architecture. In addition, data CAN be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, Logic and bit-manipulation operations that CAN all be performed in a single machine cycle. In addition, the 549 includes the control mechanisms to manage interrupts, repeated operations, and function calls. This data sheet contains the pin layouts, signal descriptions, and electrical specifications for the SMJ320LC549 DSP For additional information, see the TMS320C54x, TMS320LC54x, TMS320VC54x Fixed-Point Digital Signal Processors data sheet (literature number SPRS039). The SPRS039 is considered a family functional overview and should be used in conjunction with this data sheet. By Texas Instruments