18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTSThese 18-bit universal Bus Transceivers combine
D-type Latches and D-type Flip-Flops to allow data
flow in transparent, latched, clocked, and
clock-enabled modes.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and Clock (CLKAB and
CLKBA) inputs. The Clock CAN be controlled by the
clock-enable (CLKENAB and CLKENBA) inputs.
For A-to-B data flow, the device operates in the
transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held
at a high or low Logic level. If LEAB is low, the
A-bus data is stored in the latch Flip-Flop on the
high-to-low transition of CLKAB. Output enable
OEAB is active low. When OEAB is low, the
outputs are active. When OEAB is high, the
outputs are in the high-impedance state. By Texas Instruments
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SN54ABT16600 Pb-Free | SN54ABT16600 Cross Reference | SN54ABT16600 Schematic | SN54ABT16600 Distributor |
SN54ABT16600 Application Notes | SN54ABT16600 RoHS | SN54ABT16600 Circuits | SN54ABT16600 footprint |