OCTAL BUS TRANSCEIVERS AND REGISTERS

These devices consist of bus-transceiver SN54ABT646A SN74ABT646A circuits, D-type Flip-Flops and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal Registers Data on the A or B bus is clocked into the Registers on the low-to-high transition of the appropriate Clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that CAN be performed with the ABT646A. Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port CAN be stored in either Register or in both. The select-control (SAB and SBA) inputs CAN multiplex stored and real-time (transparent mode) data. The direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high), A data CAN be stored in one Register and/or B data CAN be stored in the other Register When an output function is disabled, the input function is still enabled and CAN be used to store and transmit data. Only one of the two buses, A or B, CAN be driven at a time. By Texas Instruments