8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

The ABT833 8-bit to 9-bit parity transceivers are designed for Communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error (ERR) output indicates whether or not an error in the B data has occurred. The output-enable (OEA and OEB) inputs CAN be used to disable the device so that the buses are effectively isolated. The ABT833 provide true data at their outputs. A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR flag. ERR is clocked into the Register on the rising edge of the Clock (CLK) input. The error flag Register is cleared with a low pulse on the clear (CLR) input. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. By Texas Instruments