These 36-bit UBTs combine D-type Latches and D-type Flip-Flops SN54ABTH32501 SN74ABTH32501 to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and Clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low Logic level. If LEAB is low, the A data is stored in the latch Flip-Flop on the low-to-high transition of CLKAB. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. Output-enable OEAB is active high. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. The output enables are complementary (OEAB is active high, and OEBA is active low). When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid Logic level. The SN54ABTH32501 is characterized for operation over the full military temperature range of 55C to 125C. The SN74ABTH32501 is characterized for operation from 40C to 85C By Texas Instruments
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SN54ABTH32501 Pinout, Pinouts
SN54ABTH32501 pinout,Pin out
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