TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES

The ACT8990 test-bus controllers (TBC) are members of the Texas Instruments SCOPE testability integrated-circuit family. This family of components supports IEEE Standard 1149.1-1990 (JTAG) boundary scan to facilitate testing of complex circuit-board assemblies. The ACT8990 differ from other SCOPE integrated circuits. Their function is to control the JTAG serial-test bus rather than being target boundary-scannable devices. The required signals of the JTAG serial-test bus test Clock (TCK), test mode select (TMS), test data input (TDI), and test data output (TDO) CAN be connected from the TBC to a target device without additional Logic This is done as a chain of IEEE Standard 1149.1-1990 boundary-scannable components that share the same serial-test bus. The TBC generates TMS and TDI signals for its target(s), receives TDO signals from its target(s), and Buffers its test Clock input (TCKI) to a test Clock output (TCKO) for distribution to its target(s). The TMS, TDI, and TDO signals CAN be connected to a target directly or via a pipeline, with a retiming delay of up to 31 bits. Since the TBC CAN be configured to generate up to six separate TMS signals [TMS (5 0)], it CAN be used to control up to six target scan paths that are connected in parallel (i.e., sharing common TCK, TDI, and TDO signals). While most operations of the TBC are synchronous to TCKI, a test-off (TOFF) input is provided for output control of the target Interface and a test-reset (TRST) input is provided for hardware/software reset of the TBC. In addition, four event [EVENT (30)] I/Os are provided for asynchronous Communication to target device(s). Each event has its own event generation/detection Logic and detected events CAN be counted by two 16-bit Counters By Texas Instruments
SN54ACT8990 's PackagesSN54ACT8990 's pdf datasheet
5962-9322801MXA CFP
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SNJ54ACT8990GB CPGA
SNJ54ACT8990HV CFP




SN54ACT8990 Pinout, Pinouts
SN54ACT8990 pinout,Pin out
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