The AHC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders CAN be used to minimize the effects of system decoding. When employed with high-speed Memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external Gates or inverters when expanding. A 24-line decoder CAN be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input CAN be used as a data input for demultiplexing applications. By Texas Instruments
SN54AHC138 's PackagesSN54AHC138 's pdf datasheet

SN54AHC138 Pinout, Pinouts
SN54AHC138 pinout,Pin out
This is one package pinout of SN54AHC138,If you need more pinouts please download SN54AHC138's pdf datasheet.

SN54AHC138 Application circuits
SN54AHC138 circuits
This is one application circuit of SN54AHC138,If you need more circuits,please download SN54AHC138's pdf datasheet.

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