DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

These devices SN54ALS112A SN74ALS112A contain two independent J-K negative-edge-triggered Flip-Flops A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the Clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the Clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile Flip-Flops CAN perform as toggle Flip-Flops by tying J and K high. The SN54ALS112A is characterized for operation over the full military temperature range of 55C to 125C. The SN74ALS112A is characterized for operation from 0C to 70C. By Texas Instruments
Part Manufacturer Description Datasheet Samples
SN54ALS112AFK Rochester Electronics LLC J-K Flip-Flop, ALS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CQCC20, CERAMIC, CC-20
SN54ALS112AJ Rochester Electronics LLC Flip Flop
SN54ALS112AJ Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-CDIP -55 to 125
SN54ALS112A 's PackagesSN54ALS112A 's pdf datasheet



SN54ALS112A Pinout, Pinouts
SN54ALS112A pinout,Pin out
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