PARALLEL-LOAD 8-BIT REGISTERS

The ALS165 are parallel-load 8-bit serial shift Registers SN54ALS165 SN74ALS165 that, when clocked, shift the data toward serial (QH and QH) outputs. Parallel-in access to each stage is provided by eight individual direct data (AH) inputs that are enabled by a low level at the shift/load (SH/LD) input. The ALS165 have a clock-inhibit function and complemented serial outputs. Clocking is accomplished by a low-to-high transition of the Clock (CLK) input while SH/LD is held high and the Clock inhibit (CLK INH) input is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplishes clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. The parallel inputs to the Register are enabled while SH/LD is low independently of the levels of the CLK, CLK INH, or serial (SER) inputs By Texas Instruments