These devices SN54ALS646 SN54ALS648 SN54AS646 SN74ALS646A SN74ALS648A SN74AS646 SN74AS648 consist of bus-transceiver circuits with 3-state or open-collector outputs, D-type Flip-Flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage Registers Data on the A or B bus is clocked into the Registers on the low-to-high transition of the appropriate Clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that CAN be performed with the octal bus transceivers and Registers Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high- impedance port may be stored in either or both Registers The select-control (SAB and SBA) inputs CAN multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data may be stored in one Register and/or B data may be stored in the other Register When an output function is disabled, the input function is still enabled and CAN be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. By Texas Instruments
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