3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUPUTS

The SN54CDC586 is a high-performance, low-skew, low-jitter Clock Driver It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the Clock output signals to the Clock input (CLKIN) signal. It is specifically designed for use with popular Microprocessors operating at speeds from 50 MHz to 100 MHz, or down to 25 MHz on outputs configured as half-frequency outputs. The SN54CDC586 operates at 3.3-V VCC and is designed to drive a properly terminated 50- transmission line. The feedback input (FBIN) is used to synchronize the output Clocks in frequency and phase to CLKIN. One of the 12 output Clocks must be fed back to FBIN for the PLL to maintain synchronization between the CLKIN input and the outputs. The output used as the feedback pin is synchronized to the same frequency as the CLKIN input. The Y outputs CAN be configured to Switch in phase and at the same frequency as CLKIN. Select inputs (SEL1, SEL0) configure up to nine Y outputs, in banks of three, to operate at one-half or double the CLKIN frequency, depending on which pin is fed back to FBIN (see Tables 1 and 2). All output-signal duty cycles are adjusted to 50%, independent of the duty cycle at CLKIN. By Texas Instruments
SN54CDC586 's PackagesSN54CDC586 's pdf datasheet



SN54CDC586 Pinout, Pinouts
SN54CDC586 pinout,Pin out
This is one package pinout of SN54CDC586,If you need more pinouts please download SN54CDC586's pdf datasheet.

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