DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

These devices SN54F109 SN74F109 contain two independent J-K positive-edge-triggered Flip-Flops A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the Clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the Clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile Flip-Flops CAN perform as toggle Flip-Flops by grounding K and trying J high. They also CAN perform as D-type Flip-Flops if J and K are tied together. The SN54F109 is characterized for operation over the full military temperature range of 55C to 125C. The SN74F109 is characterized for operation from 0C to 70C. By Texas Instruments
SN54F109 's PackagesSN54F109 's pdf datasheet
SNJ54F109FK LCCC
SNJ54F109J DIP
SNJ54F109W CFP




SN54F109 Pinout, Pinouts
SN54F109 pinout,Pin out
This is one package pinout of SN54F109,If you need more pinouts please download SN54F109's pdf datasheet.

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