18-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERSThese 18-bit Bus Transceivers SN54GTL16612 SN74GTL16612 combine D-type
Latches and D-type Flip-Flops to allow data flow in
transparent, latched, and clocked modes.
The B port operates at GTL levels while the A port
and control inputs are compatible with LVTTL and
5-V TTL Logic levels.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and Clock (CLKAB and
CLKBA) inputs. The Clock or latch-enable CAN be
controlled by the clock-enable (CEAB and CEBA)
inputs. For A-to-B data flow, the devices operate
in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CEAB is low
and CLKAB is held at a high or low Logic level. If
LEAB is low, the A-bus data is stored in the
latch Flip-Flop on the low-to-high transition of
CLKAB if CEAB is also low. OEAB is active low.
When OEAB is low, the outputs are active. When
OEAB is high, the outputs are in the
high-impedance state. Data flow for B to A is
similar to that for A to B, but uses OEBA, LEBA,
CLKBA, and CEBA. By Texas Instruments
|
|
SN54GTL16612 Pb-Free | SN54GTL16612 Cross Reference | SN54GTL16612 Schematic | SN54GTL16612 Distributor |
SN54GTL16612 Application Notes | SN54GTL16612 RoHS | SN54GTL16612 Circuits | SN54GTL16612 footprint |