18-BIT LVTTL-TO-GTL/GTL BUS TRANSCEIVERS

The GTL16622A devices SN54GTL16622A SN74GTL16622A are 18-bit registered Bus Transceivers that provide LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. They are partitioned as two separate 9-bit transceivers with individual clock-enable controls and contain D-type Flip-Flops for temporary storage of data flowing in either direction. The devices provide an Interface between cards operating at LVTTL Logic levels and a Backplane operating at GTL/GTL+ signal levels. Higher speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and output edge control (OEC). The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL Logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port. By Texas Instruments
SN54GTL16622A 's PackagesSN54GTL16622A 's pdf datasheet



SN54GTL16622A Pinout, Pinouts
SN54GTL16622A pinout,Pin out
This is one package pinout of SN54GTL16622A,If you need more pinouts please download SN54GTL16622A's pdf datasheet.

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