Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear

These devices contain two independent J-K negative-edge-triggered Flip-Flops A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the Clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the Clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile Flip-Flops CAN perform as toggle Flip-Flops by tying J and K high. The SN54LS112A and SN54S112 are characterized for operation over the full military temperature range of -55°C to 125°C. By Texas Instruments
Part Manufacturer Description Datasheet Samples
SN54LS112AFK Rochester Electronics LLC J-K Flip-Flop, LS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CQCC20, CERAMIC, CC-20
SN54LS112AW Rochester Electronics LLC J-K Flip-Flop, LS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CDFP16, CERAMIC, FP-16
SN54LS112AJ Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CDIP -55 to 125
SN54LS112A 's PackagesSN54LS112A 's pdf datasheet
SN54LS112AJ
SNJ54LS112AFK
SNJ54LS112AJ
SNJ54LS112AW
JM38510-07102BEA
JM38510-07102BFA
JM38510-30103B2A
JM38510-30103BEA
JM38510-30103BFA
SN54S112J
SNJ54S112FK
SNJ54S112J




SN54LS112A Pinout, Pinouts
SN54LS112A pinout,Pin out
This is one package pinout of SN54LS112A,If you need more pinouts please download SN54LS112A's pdf datasheet.

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SN54LS112A Application Notes SN54LS112A RoHS SN54LS112A Circuits SN54LS112A footprint
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