These devices feature AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated serial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new data and resets the first Flip-Flop to the low level at the next Clock pulse. A high-level input enables the other input, which then determines the state of the first Flip-Flop Data at the serial inputs CAN be changed while the Clock is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of the Clock (CLK) input. By Texas Instruments
SN54LV164A 's PackagesSN54LV164A 's pdf datasheet

SN54LV164A Pinout, Pinouts
SN54LV164A pinout,Pin out
This is one package pinout of SN54LV164A,If you need more pinouts please download SN54LV164A's pdf datasheet.

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