OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

The SN54LVC573A octal transparent D-type latch SN54LVC573A SN74LVC573A is designed for 2.7-V to 3.6-V VCC operation and the SN74LVC573A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing Buffer Registers input/output (I/O) ports, bidirectional bus drivers, and working Registers While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the Logic levels at the D inputs. A buffered output-enable (OE) input CAN be used to place the eight outputs in either a normal Logic state (high or low Logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without Interface or pullup components. OE does not affect the internal operations of the Latches Old data CAN be retained or new data CAN be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs CAN be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. By Texas Instruments
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SN54LVC573A Pinout, Pinouts
SN54LVC573A pinout,Pin out
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