These octal Latches SN54LVTH373 SN74LVTH373 are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL Interface to a 5-V system environment. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the Logic levels set up at the D inputs. A buffered output-enable (OE) input CAN be used to place the eight outputs in either a normal Logic state (high or low Logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for Interface or pullup components. OE does not affect the internal operations of the Latches Old data CAN be retained or new data CAN be entered while the outputs are in the high-impedance state. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. By Texas Instruments
SN54LVTH373 's PackagesSN54LVTH373 's pdf datasheet

SN54LVTH373 Pinout, Pinouts
SN54LVTH373 pinout,Pin out
This is one package pinout of SN54LVTH373,If you need more pinouts please download SN54LVTH373's pdf datasheet.

SN54LVTH373 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

SN54LVTH373 Pb-Free SN54LVTH373 Cross Reference SN54LVTH373 Schematic SN54LVTH373 Distributor
SN54LVTH373 Application Notes SN54LVTH373 RoHS SN54LVTH373 Circuits SN54LVTH373 footprint
Hot categories