These octal Flip-Flops SN54LVTH574 SN74LVTH574 are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL Interface to a 5-V system environment. The eight Flip-Flops of the LVTH574 are edge-triggered D-type Flip-Flops On the positive transition of the Clock (CLK) input, the Q outputs are set to the Logic levels set up at the data (D) inputs. A buffered output-enable (OE) input CAN be used to place the eight outputs in either a normal Logic state (high or low Logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for Interface or pullup components. OE does not affect the internal operations of the Flip-Flops Old data CAN be retained or new data CAN be entered while the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid Logic level. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. By Texas Instruments
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SN54LVTH574 Pinout, Pinouts
SN54LVTH574 pinout,Pin out
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