1:4 LVDS Clock Fanout Buffer

The SN65LVDS104 and SN65LVDS105 are a differential line receiver and a LVTTL input (respectively) connected to four differential Line Drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDs as specified in EIA/TIA-644 is a data signaling technique that offers low-power, low-noise coupling, and switching speeds to transmit data at relatively long distances. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)
The SN65LVDS104 and SN65LVDS105 are characterized for operation from 40C to 85C.
The SN65LVDS104 and SN65LVDS105 are members of a family of LVDs repeaters. A brief overview of the family is provided in the table below.
By Texas Instruments
SN65LVDS104 's PackagesSN65LVDS104 's pdf datasheet
SN65LVDS104D SOIC
SN65LVDS104DG4 SOIC
SN65LVDS104DR SOIC
SN65LVDS104DRG4 SOIC
SN65LVDS104PW TSSOP
SN65LVDS104PWG4 TSSOP
SN65LVDS104PWR TSSOP
SN65LVDS104PWRG4 TSSOP

SN65LVDS104 pdf datasheet download
SN65LVDS104 Pinout, Pinouts
SN65LVDS104 pinout,Pin out
This is one package pinout of SN65LVDS104,If you need more pinouts please download SN65LVDS104's pdf datasheet.

SN65LVDS104 Application circuits
SN65LVDS104 circuits
This is one application circuit of SN65LVDS104,If you need more circuits,please download SN65LVDS104's pdf datasheet.


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