1 LVTTL:4 LVDS Clock Fanout Buffer
The SN65LVDS104 and SN65LVDS105 are a differential line receiver and a LVTTL input (respectively) connected to four differential Line Drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDs as specified in EIA/TIA-644 is a data signaling technique that offers low-power, low-noise coupling, and switching speeds to transmit data at relatively long distances. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)
The SN65LVDS104 and SN65LVDS105 are characterized for operation from 40C to 85C.
The SN65LVDS104 and SN65LVDS105 are members of a family of LVDs repeaters. A brief overview of the family is provided in the table below.
By Texas Instruments
|SN65LVDS105 Pb-Free||SN65LVDS105 Cross Reference||SN65LVDS105 Schematic||SN65LVDS105 Distributor|
|SN65LVDS105 Application Notes||SN65LVDS105 RoHS||SN65LVDS105 Circuits||SN65LVDS105 footprint|