1 LVTTL:4 LVDS Clock Fanout Buffer

The SN65LVDS104 and SN65LVDS105 are a differential line receiver and a LVTTL input (respectively) connected to four differential Line Drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDs as specified in EIA/TIA-644 is a data signaling technique that offers low-power, low-noise coupling, and switching speeds to transmit data at relatively long distances. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)
The SN65LVDS104 and SN65LVDS105 are characterized for operation from 40C to 85C.
The SN65LVDS104 and SN65LVDS105 are members of a family of LVDs repeaters. A brief overview of the family is provided in the table below.
By Texas Instruments
SN65LVDS105 's PackagesSN65LVDS105 's pdf datasheet
SN65LVDS105D SOIC
SN65LVDS105DG4 SOIC
SN65LVDS105DR SOIC
SN65LVDS105DRG4 SOIC
SN65LVDS105PW TSSOP
SN65LVDS105PWG4 TSSOP
SN65LVDS105PWR TSSOP
SN65LVDS105PWRG4 TSSOP

SN65LVDS105 pdf datasheet download
SN65LVDS105 Pinout, Pinouts
SN65LVDS105 pinout,Pin out
This is one package pinout of SN65LVDS105,If you need more pinouts please download SN65LVDS105's pdf datasheet.

SN65LVDS105 Application circuits
SN65LVDS105 circuits
This is one application circuit of SN65LVDS105,If you need more circuits,please download SN65LVDS105's pdf datasheet.


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