1:8 LVDS Clock Fanout Buffer

The SN65LVDS108 is configured as one differential line receiver connected to eight differential Line Drivers Individual output enables are provided for each output and an additional enable is provided for all outputs.
The line receivers and Line Drivers implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDs as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise emission, high noise immunity, and high switching speeds. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)
The intended application of this device, and the LVDs signaling technique, is for point-to-point or point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, Backplanes or cables. The large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced signaling, provides extremely precise Timing alignment of the signals being repeated from the inputs. This is particularly advantageous for implementing system Clock or data distribution trees.
The SN65LVDS108 is characterized for operation from 40C to 85C.
By Texas Instruments
SN65LVDS108 's PackagesSN65LVDS108 's pdf datasheet

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SN65LVDS108 Pinout, Pinouts
SN65LVDS108 pinout,Pin out
This is one package pinout of SN65LVDS108,If you need more pinouts please download SN65LVDS108's pdf datasheet.

SN65LVDS108 Application circuits
SN65LVDS108 circuits
This is one application circuit of SN65LVDS108,If you need more circuits,please download SN65LVDS108's pdf datasheet.

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