1:8 LVDS Clock Fanout Buffer
The SN65LVDS108 is configured as one differential line receiver connected to eight differential Line Drivers Individual output enables are provided for each output and an additional enable is provided for all outputs.
The line receivers and Line Drivers implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDs as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise emission, high noise immunity, and high switching speeds. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)
The intended application of this device, and the LVDs signaling technique, is for point-to-point or point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, Backplanes or cables. The large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced signaling, provides extremely precise Timing alignment of the signals being repeated from the inputs. This is particularly advantageous for implementing system Clock or data distribution trees.
The SN65LVDS108 is characterized for operation from 40C to 85C.
By Texas Instruments
|SN65LVDS108DBTRG4||Texas Instruments||1:8 LVDS Clock Fanout Buffer 38-TSSOP -40 to 85|
|SN65LVDS108DBT||Texas Instruments||1:8 LVDS Clock Fanout Buffer 38-TSSOP -40 to 85|
|SN65LVDS108DBTR||Texas Instruments||1:8 LVDS Clock Fanout Buffer 38-TSSOP -40 to 85|
|SN65LVDS108DBTG4||Texas Instruments||1:8 LVDS Clock Fanout Buffer 38-TSSOP -40 to 85|
|SN65LVDS108 Pb-Free||SN65LVDS108 Cross Reference||SN65LVDS108 Schematic||SN65LVDS108 Distributor|
|SN65LVDS108 Application Notes||SN65LVDS108 RoHS||SN65LVDS108 Circuits||SN65LVDS108 footprint|