The SN65LVDS116 is one differential line reciever connected to sixteen differential Line Drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDs as specified in EIA/TIA-644, is a data signaling technique that offers the low-power, low-noise coupling, and switching speeds to transmit data at speeds up to 622 Mbps and relatively long distances. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.) The intended application of this device and signaling technique is for point-to-point or multidrop baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed circuit board traces, Backplanes or cables. The large number of drivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise Timing alignment of the signals repeated from the input. This is particularly advantageous in system Clock Distribution The SN65LVDS116 is characterised for operation from 40C to 85C. By Texas Instruments
Part Manufacturer Description Datasheet Samples
SN65LVDS116DGG Texas Instruments 1:16 LVDS Clock Fanout Buffer 64-TSSOP -40 to 85
SN65LVDS116DGGG4 Texas Instruments 1:16 LVDS Clock Fanout Buffer 64-TSSOP -40 to 85
SN65LVDS116DGGR Texas Instruments 1:16 LVDS Clock Fanout Buffer 64-TSSOP -40 to 85
SN65LVDS116 's PackagesSN65LVDS116 's pdf datasheet

SN65LVDS116 Pinout, Pinouts
SN65LVDS116 pinout,Pin out
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