PARALLEL-LOAD-8-BIT SHIFT REGISTERS

The 165 and LS165A are 8-bit serial shift Registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. These Registers also feature gated Clock (CLK) inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design. Clocking is accomplished through a two-input positive-NOR Gate permitting one input to be used as a clock-inhibit function. Holding either of the Clock inputs high inhibits clocking, and holding either Clock input low with SH/LD high enables the other Clock input. Clock inhibit (CLK INH) should be changed to the high level only while CLK is high. Parallel loading is inhibited as long as SH/LD is high. Data at the parallel inputs are loaded directly into the Register while SH/LD is low, independently of the levels of CLK, CLK INH, or serial (SER) inputs. By Texas Instruments
SN744165 's PackagesSN744165 's pdf datasheet
SN74165N PDIP
SN54165
SN54LS165A




SN744165 Pinout, Pinouts
SN744165 pinout,Pin out
This is one package pinout of SN744165,If you need more pinouts please download SN744165's pdf datasheet.

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