Synchronous 6-bit Binary Rate Multiplier

These monolithic, fully synchronous, programmable Counters utilize Series 54/74 TTL circuitry to achieve 32-megahertz typical maximum operating frequencies. These six-bit serial binary Counters feature buffered Clock clear, and enable inputs to control the operation of the Counter and a strobe input to enable or inhibit the rate input/decoding AND-OR-INVERT Gates The outputs have additional gating for cascading and transferring unity-count rates.
The Counter is enabled when the clear, strobe, and enable inputs are low. With the Counter enabled, the output frequency is equal to the input frequency multiplied by the rate input M and divided by 64, ie.:
When the rate input is binary 0 (all rate inputs low), Z remains high. In order to cascade devices to perform 12-bit rate multiplication, the enable output is connected to the enable and strobe inputs of the next stage, the Z output of each stage is connected to the unity/cascade input of the other stage, and the sub-multiple frequency is taken from the Y output.
The unity/cascade input, when connected to the Clock input, may be utilized to pass the Clock frequency (inverted) to the Y output when the rate input/decoding Gates are inhibited by the strobe. The unity/cascade input may also be used as a control for the Y output.
By Texas Instruments
Part Manufacturer Description Datasheet Samples
SN7497N Texas Instruments Synchronous 6-bit binary rate multiplier 16-PDIP 0 to 70
SN7497N3 Texas Instruments Synchronous 6-bit binary rate multiplier 16-PDIP 0 to 70
SN7497NE4 Texas Instruments Synchronous 6-bit binary rate multiplier 16-PDIP 0 to 70
SN7497 's PackagesSN7497 's pdf datasheet
SN7497N PDIP
SN7497N3 PDIP
SN7497NE4 PDIP




SN7497 Pinout, Pinouts
SN7497 pinout,Pin out
This is one package pinout of SN7497,If you need more pinouts please download SN7497's pdf datasheet.

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