Dual 8-Bit To 9-Bit Parity Transceivers

The SN74ABT16853 dual 8-bit to 9-bit parity transceivers are designed for Communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus, with its corresponding parity bit, the open-collector parity-error () output indicates whether or not an error in the B data has occurred. The output-enable (and ) inputs CAN be used to disable the device so that the buses are effectively isolated. The 'ABT16853 provide true data at the outputs.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the flag. The parity-error output CAN be passed, sampled, stored, or cleared from the latch using the latch-enable () and clear () control inputs. When both and are low, data is transferred from the A bus to the B bus, and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability.
To ensure the high-impedance state during power up or power down, should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16853 is characterized for operation over the full military temperature range of -55?C to 125?C. The SN74ABT16853 is characterized for operation from -40?C to 85?C.
By Texas Instruments