The SN74ABT3611 is a high-speed, low-power BiCMOS clocked FIFO memory. It supports Clock frequencies up to 67 MHz and has read access times as fast as 10 ns. A 64 36 dual-port SRAM FIFO Buffers data from port A to port B. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port takes place through two 36-bit mailbox Registers Each mailbox Register has a flag to signal when new mail has been stored. Parity is checked passively on each port and CAN be ignored if not desired. Parity generation CAN be selected for data read from each port. Two or more devices are used in parallel to create wider datapaths. The SN74ABT3611 is a clocked FIFO which means each port employs a synchronous Interface All data transfers through a port are gated to the low-to-high transition of a port Clock by enable signals. The Clocks for each port are independent of one another and CAN be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional Interface between Microprocessors and/or buses with synchronous control. The full flag (FF) and almost-full (AF) flag of the FIFO are two-stage synchronized to the port Clock that writes data to its array (CLKA). The empty flag (EF) and almost-empty (AE) flag of the FIFO are two-stage synchronized to the port Clock that reads data from its array. By Texas Instruments
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SN74ABT3611 Pinout, Pinouts
SN74ABT3611 pinout,Pin out
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