64 ?? 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPINGThe SN74ABT3613 is a high-speed, low-power BiCMOS clocked FIFO memory. It supports Clock frequencies
up to 67 MHz and has read-access times as fast as 10 ns. A 64 36 dual-port SRAM FIFO in this device Buffers
data from port A to port B. The FIFO has flags to indicate empty and full conditions and two programmable flags
(almost full and almost empty) to indicate when a selected number of words is stored in memory. FIFO data on
port B CAN be output in 36-bit, 18-bit, and 9-bit formats, with a choice of big- or little-endian configurations. Three
modes of byte-order swapping are possible with any bus-size selection. Communication between each port CAN
bypass the FIFO via two 36-bit mailbox Registers Each mailbox Register has a flag to signal when new mail has
been stored. Parity is checked passively on each port and CAN be ignored if not desired. Parity generation CAN
be selected for data read from each port.
The SN74ABT3613 is a clocked FIFO which means each port employs a synchronous Interface All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port Clock by enable
signals. The continuous Clocks for each port are independent of one another and CAN be asynchronous or
coincident. The enables for each port are arranged to provide a simple Interface between Microprocessors
and/or buses controlled by a synchronous Interface
The full flag (FF) and almost-full (AF) flag of a FIFO are two-stage synchronized to the port Clock that writes data
to its array. The empty flag (EF) and almost-empty (AE) flag of a FIFO are two-stage synchronized to the port
Clock that reads data from its array. By Texas Instruments
|
|
SN74ABT3613 Pb-Free | SN74ABT3613 Cross Reference | SN74ABT3613 Schematic | SN74ABT3613 Distributor |
SN74ABT3613 Application Notes | SN74ABT3613 RoHS | SN74ABT3613 Circuits | SN74ABT3613 footprint |