64 X 4 Asynchronous FIFO Memory
The SN74ALS236 is a 256-bit memory utilizing advanced low-power Schottky IMPACTTM technology. It features high speed with fast fall-through times and is organized as 64 words by 4 bits.
A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ALS236 is designed to process data at rates up to 30 MHz in a bit-parallel format, word by word.
Data is written into memory on the rising edge of the shift-in (SI) input. When SI goes low, the first data word ripples through to the output (see Figure 1). As the FIFO fills up, the data words stack up in the order they were written. When the FIFO is full, additional shift-in pulses have no effect. Data is shifted out of memory on the falling
edge of the shift-out (SO) input (see Figure 2). When the FIFO is empty, additional SO pulses have no effect. The last data word remains at the outputs until a new word falls through or reset (RST) goes low.
Status of the SN74ALS236 FIFO memory is monitored by the output-ready (OR) and input-ready (IR) flags. When OR is high, valid data is available at the outputs. OR is low when SO is high and stays low when the FIFO is empty. IR is high when the inputs are ready to receive more data. IR is low when SI is high and stays low when the FIFO is full.
When the FIFO is empty, input data is shifted to the output automatically when SI goes low. If SO is held high during this time, the OR flag pulses high, indicating valid data at the outputs (see Figure 3).
When the FIFO is full, data is shifted in automatically by holding SI high and taking SO low. One propagation delay after SO goes low, IR goes high. If SI is still high when IR goes high, data at the inputs is automatically shifted in. Since IR is normally low when the FIFO is full and SI is high, only a high-level pulse is seen on the IR output (see Figure 4).
The FIFO must be reset after power up with a low-level pulse on the master reset (RST) input. This sets IR high and OR low, signifying that the FIFO is empty. Resetting the FIFO sets the outputs to a low Logic level (see Figure 1). If SI is high when RST goes high, the input data is shifted in and IR goes low and remains low until SI goes low. If SI goes low before RST goes high, the input data is not shifted in and IR goes high. Data outputs are noninverting with respect to the data inputs.
The SN74ALS236 is characterized for operation from 0C to 70C.
By Texas Instruments
|SN74ALS236N||Texas Instruments||64 x 4 asynchronous FIFO memory 16-PDIP 0 to 70|
|SN74ALS236FN||Texas Instruments||64X4 OTHER FIFO, 22ns, PQCC20, PLASTIC, LCC-20|
|SN74ALS236FNR||Texas Instruments||64X4 OTHER FIFO, 22ns, PQCC20, PLASTIC, LCC-20|
|SN74ALS236DWR||Texas Instruments||64X4 OTHER FIFO, 22ns, PDSO16, PLASTIC, SO-16|
|SN74ALS236DW||Texas Instruments||64X4 OTHER FIFO, 22ns, PDSO16, PLASTIC, SO-16|
|SN74ALS236D||Texas Instruments||64X4 OTHER FIFO, 22ns, PDSO16|
|SN74ALS236 Pb-Free||SN74ALS236 Cross Reference||SN74ALS236 Schematic||SN74ALS236 Distributor|
|SN74ALS236 Application Notes||SN74ALS236 RoHS||SN74ALS236 Circuits||SN74ALS236 footprint|