12-Bit To 24-Bit Multiplexed Bus Exchanger With 3-State Outputs

This 12-bit to 24-bit Bus Exchanger is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16271 is intended for applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. This device is particularly suitable as an Interface between conventional DRAMs and high-speed Microprocessors
A data is stored in the internal A-to-B Registers on the low-to-high transition of the Clock (CLK) input, provided that the clock-enable (CLKENA) inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port.
Transparent Latches in the B-to-A path allow asynchronous operation to maximize memory access throughput. These Latches transfer data when the latch-enable (LE) inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. Data flow is controlled by the active-low output enables (OEA, OEB).
To ensure the high-impedance state during power up or power down, the output enables should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid Logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
By Texas Instruments