18-Bit Registered Bus Transceiver With 3-State Outputs

This 18-bit universal Bus Transceiver SN74ALVCH16525 is designed for 1.65-V to 3.6-V VCC operation.
Data flow in each direction is controlled by output-enable (OEAB and OEBA) and clock-enable (CLKENAB and CLKENBA) inputs. For the A-to-B data flow, the data flows through a single Register The B-to-A data CAN flow through a four-stage pipeline Register path, or through a single Register path, depending on the state of the select (SEL) input.
Data is stored in the internal Registers on the low-to-high transition of the Clock (CLK) input, provided that the appropriate CLKEN inputs are low. The A-to-B data transfer is synchronized to the CLKAB input, and B-to-A data transfer is synchronized with the CLK1BA and CLK2BA inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid Logic level.
The SN74ALVCH16525 is characterized for operation from ?40C to 85C.
By Texas Instruments