3.3-V 12-Bit Universal Bus Driver With Parity Checker And Dual 3-State Outputs

This 12-bit universal bus driver is designed for 2.3-V to 3.6-V VCC operation.
The SN74ALVCH16903 has dual outputs and CAN operate as a Buffer or an edge-triggered Register In both modes, parity is checked on APAR, which arrives one cycle after the data to which it applies. The YERR output, which is produced one cycle after APAR, is open drain.
MODE selects one of the two data paths. When MODE is low, the device operates as an edge-triggered Register On the positive transition of the Clock (CLK) input and when the clock-enable (CLKEN) input is low, data set up at the A inputs is stored in the internal Registers On the positive transition of CLK and when CLKEN is high, only data set up at the 9A-12A inputs is stored in their internal Registers When MODE is high, the device operates as a Buffer and data at the A inputs passes directly to the outputs. 11A/YERREN serves a dual purpose; it acts as a normal data bit and also enables YERR data to be clocked into the YERR output Register
When used as a single device, parity output enable (PAROE) must be tied high; when parity input/output (PARI/O) is low, even parity is selected and when PARI/O is high, odd parity is selected. When used in pairs and PAROE is low, the parity sum is output on PARI/O for cascading to the second SN74ALVCH16903. When used in pairs and PAROE is high, PARI/O accepts a partial parity sum from the first SN74ALVCH16903.
A buffered output-enable (OE) input CAN be used to place the 24 outputs and YERR in either a normal Logic state (high or low Logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for Interface or pullup components.
OE does not affect the internal operation of the device. Old data CAN be retained or new data CAN be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid Logic level.
The SN74ALVCH16903 is characterized for operation from 0C to 70C.
By Texas Instruments
Part Manufacturer Description Datasheet Samples
SN74ALVCH16903DGVR Texas Instruments ALVC/VCX/A SERIES, 12-BIT DRIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TVSOP-56
SN74ALVCH16903DGGR Texas Instruments ALVC/VCX/A SERIES, 12-BIT DRIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56
SN74ALVCH16903DL Texas Instruments 3.3-V 12-Bit Universal Bus Driver with Parity Checker and Dual 3-State Outputs 56-SSOP -40 to 85
SN74ALVCH16903 's PackagesSN74ALVCH16903 's pdf datasheet
74ALVCH16903DGGRE4 TSSOP
74ALVCH16903DGGRG4 TSSOP
74ALVCH16903DGVRE4 TVSOP
74ALVCH16903DGVRG4 TVSOP
74ALVCH16903DLG4 SSOP
74ALVCH16903DLRG4 SSOP
SN74ALVCH16903DGGR TSSOP
SN74ALVCH16903DGVR TVSOP
SN74ALVCH16903DL SSOP
SN74ALVCH16903DLR SSOP




SN74ALVCH16903 Pinout, Pinouts
SN74ALVCH16903 pinout,Pin out
This is one package pinout of SN74ALVCH16903,If you need more pinouts please download SN74ALVCH16903's pdf datasheet.

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