12-Bit To 24-Bit Registered Bus Exchanger With 3-State Outputs

A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC TM ) Circuitry Technology and Applications, literature number SCEA009.
This 12-bit to 24-bit registered Bus Exchanger is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation.
The SN74AVC16269 is used in applications in which two separate ports must be multiplexed onto, or demultiplexed from, a single port. The device is particularly suitable as an Interface between synchronous DRAMs and high-speed Microprocessors
Data is stored in the internal B-port Registers on the low-to-high transition of the Clock (CLK) input when the appropriate clock-enable (CLKENA) inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port. For data transfer in the B-to-A direction, a single storage Register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The Register on the A output permits the fastest possible data transfer, thus extending the period during which the data is valid on the bus.
The control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled by the active-low output enables (OEA, OEB1, OEB2).
To ensure the high-impedance state during power up or power down, a Clock pulse should be applied as soon as possible, and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE being routed through a Register the active state of the outputs cannot be determined prior to the arrival of the first Clock pulse.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74AVC16269 is characterized for operation from -40C to 85C.
By Texas Instruments
Part Manufacturer Description Datasheet Samples
SN74AVC16269DGVR Texas Instruments AVC SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TVSOP-56
SN74AVC16269DGGR Texas Instruments AVC SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56
SN74AVC16269 's PackagesSN74AVC16269 's pdf datasheet
74AVC16269DGGRE4 TSSOP
74AVC16269DGGRG4 TSSOP
74AVC16269DGVRE4 TVSOP
74AVC16269DGVRG4 TVSOP
SN74AVC16269DGGR TSSOP
SN74AVC16269DGVR TVSOP




SN74AVC16269 Pinout, Pinouts
SN74AVC16269 pinout,Pin out
This is one package pinout of SN74AVC16269,If you need more pinouts please download SN74AVC16269's pdf datasheet.

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