14-Bit To 28-Bit HSTL-To-LVTTL Memory Address Latch
This 14-bit to 28-bit D-type latch is designed for 3.15-V to 3.45-V VCC operation. HSTL levels are expected on the inputs. LVTTL levels are driven on the Q outputs.
All outputs are designed to sink up to 12 mA and include 25- series resistors to reduce overshoot and undershoot.
The SN74HSTL162822 is particularly suitable for driving an address bus to two banks of memory. Each bank of 14 outputs is controlled with its own latch-enable () input.
Each of the 14 data (D) inputs is tied to the inputs of two D-type Latches which provide true data at the outputs. While LE is low, the outputs (Q) of the corresponding 14 Latches follow the D inputs. When is taken high, the Q outputs are latched at the levels set up at the D inputs.
The SN74HSTL162822 is characterized for operation from -40?C to 90?C.
By Texas Instruments
|SN74HSTL162822DGGR||Texas Instruments||TTL/H/L SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64|
|SN74HSTL162822 Pb-Free||SN74HSTL162822 Cross Reference||SN74HSTL162822 Schematic||SN74HSTL162822 Distributor|
|SN74HSTL162822 Application Notes||SN74HSTL162822 RoHS||SN74HSTL162822 Circuits||SN74HSTL162822 footprint|