Dual 4-bit Addressable Latch ,

The SN54LS256 SN74LS256 SN74LS256 is a Dual 4-Bit Addressable Latch with common control inputs; these include two Address inputs (A0, A1), an active LOW Enable input (E) and an active LOW Clear input (CL). Each latch has a Data input (D) and four outputs (Q0Q3). When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs (Q0Q3) are LOW. Dual 4-channel demultiplexing occurs when the (CL) and E are both LOW. When CL is HIGH and E is LOW, the selected output (Q0Q3), determined by the Address inputs, follows D. When the E goes HIGH, the contents of the latch are stored. When operating in the addressable latch mode (E=LOW, CL=HIGH), changing more than one bit of the Address (A0, A1) could impose a transient wrong address. Therefore, this should be done only while in the memory mode (E=CL=HIGH). By Freescale Semiconductor, Inc
SN74LS256 's PackagesSN74LS256 's pdf datasheet
SN54LS256J
SN74LS256N
SN54LS256




SN74LS256 Pinout, Pinouts
SN74LS256 pinout,Pin out
This is one package pinout of SN74LS256,If you need more pinouts please download SN74LS256's pdf datasheet.

SN74LS256 Application circuits
SN74LS256 circuits
This is one application circuit of SN74LS256,If you need more circuits,please download SN74LS256's pdf datasheet.


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SN74LS256 Application Notes SN74LS256 RoHS SN74LS256 Circuits SN74LS256 footprint
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