3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers
The LVTH18512 and LVTH182512 scan test devices with 18-bit universal Bus Transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) Interface
Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL Interface to a 5-V system environment.
In the normal mode, these devices are 18-bit universal Bus Transceivers that combine D-type Latches and D-type Flip-Flops to allow data flow in transparent, latched, or clocked modes. They CAN be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry CAN be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETM universal Bus Transceivers
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and Clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched while CLKAB is held at a static low or high Logic level. Otherwise, if LEAB is low, A data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow but uses the OEBA, LEBA, and CLKBA inputs.
In the test mode, the normal operation of the SCOPETM universal Bus Transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test Clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP Interface
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid Logic level.
The B-port outputs of 'LVTH182512, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.
The SN54LVTH18512 and SN54LVTH182512 are characterized for operation over the full military temperature range of -55C to 125C. The SN74LVTH18512 and SN74LVTH182512 are characterized for operation from -40C to 85C.
By Texas Instruments
|SN74LVTH182512DGGR||Texas Instruments||3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers 64-TSSOP -40 to 85|
|SN74LVTH182512DGG||Texas Instruments||LVT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64|
|V62/04730-01XE||Texas Instruments||Enhanced Product 3.3-V Abt Scan Test Devices With 18-Bit Universal Bus Transceivers 64-TSSOP -40 to 85|
|8V182512IDGGREP||Texas Instruments||Enhanced Product 3.3-V Abt Scan Test Devices With 18-Bit Universal Bus Transceivers 64-TSSOP -40 to 85|
|SN74LVTH182512 Pb-Free||SN74LVTH182512 Cross Reference||SN74LVTH182512 Schematic||SN74LVTH182512 Distributor|
|SN74LVTH182512 Application Notes||SN74LVTH182512 RoHS||SN74LVTH182512 Circuits||SN74LVTH182512 footprint|