3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers
The LVTH18502A and LVTH182502A scan test devices with 18-bit universal Bus Transceivers are members of the Texas Instruments SCOPE? testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) Interface
Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL Interface to a 5-V system environment.
In the normal mode, these devices are 18-bit universal Bus Transceivers that combine with D-type Latches and D-type Flip-Flops they allow data to flow in the transparent, latched, or clocked modes. Another use is as two 9-bit transceivers or one 18-bit transceiver. The test circuitry CAN be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal Bus Transceivers
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and Clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high Logic level. Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the OEBA, LEBA, and CLKBA inputs.
In the test mode, the normal operation of the SCOPE universal Bus Transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test Clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudorandom pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP Interface
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid Logic level.
The B-port outputs of ?LVTH182502A, which are designed to source or sink up to 12 mA, include 25- series resistors to reduce overshoot and undershoot.
The SN54LVTH18502A and SN54LVTH182502A are characterized for operation over the full military temperature range of ?55C to 125C. The SN74LVTH18502A and SN74LVTH182502A are characterized for operation from ?40C to 85C.
By Texas Instruments
|SN74LVTH18502APMR||Texas Instruments||3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers 64-LQFP -40 to 85|
|SN74LVTH18502APMG4||Texas Instruments||3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers 64-LQFP -40 to 85|
|SN74LVTH18502APM||Texas Instruments||3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers 64-LQFP -40 to 85|
|SN74LVTH18502A Pb-Free||SN74LVTH18502A Cross Reference||SN74LVTH18502A Schematic||SN74LVTH18502A Distributor|
|SN74LVTH18502A Application Notes||SN74LVTH18502A RoHS||SN74LVTH18502A Circuits||SN74LVTH18502A footprint|