3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVER WITH BOUNDARY SCAN

The SN74LVTH18511 is an 18-bit universal Bus Transceiver with boundary scan. This device supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) Interface
Additionally, this device is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL Interface to a 5-V system environment.
In the normal mode, this device is an 18-bit UBT that combines D-type Latches and D-type Flip-Flops to allow data flow in transparent, latched, or clocked modes. It CAN be used either as two 9-bit transceivers or one 18-bit transceiver. Activating the TAP in the normal mode does not affect the functional operation of the UBT.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and Clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched while CLKAB is held at a static low or high Logic level. Otherwise, if LEAB is low, A data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the OEBA, LEBA, and CLKBA inputs.
In the test mode, the normal operation of the UBT is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary scan test operations according to the protocol described in IEEE Std 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test Clock (TCK). All testing and scan operations are synchronized to the TAP Interface
Active bus-hold circuitry holds unused or undriven inputs at a valid Logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
By Texas Instruments
SN74LVTH18511 's PackagesSN74LVTH18511 's pdf datasheet
74LVTH18511DGGRE4 TSSOP
74LVTH18511DGGRG4 TSSOP
SN74LVTH18511DGGR TSSOP

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SN74LVTH18511 Pinout, Pinouts
SN74LVTH18511 pinout,Pin out
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