28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS PARITY TEST ONE PAIR TO FOUR PAIR DIFFERENTIAL CLOCK PLL DRIVER

This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering Clock Driver with parity is designed for operation on DDR3 registered DIMMs with with V DD of 1.5 V and on DDR3L registered DIMMs with V DD of 1.35 V. The SN74SSQEA32882 implements different power-saving mechanisms to reduce thermal power dissipation and to support system power-down states. Power consumption is further reduced by disabling unused outputs. All inputs are 1.5V and 1.35V CMOS-compatible. All outputs are optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications. Clock outputs Yn and Yn and control net outputs DxCKEn, DxCSn , and DxODTn CAN each be driven with a different strength and skew to optimize signal integrity, compensate for different loading, and balance signal travel speed. The SN74SSQEA32882 has two basic modes of operation associated with the Quad Chip Select Enable ( QCSEN ) input. By Texas Instruments
Part Manufacturer Description Datasheet Samples
SN74SSQEA32882ZALR Texas Instruments JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85
SN74SSQEA32882 's PackagesSN74SSQEA32882 's pdf datasheet
SN74SSQEA32882ZALR




SN74SSQEA32882 Pinout, Pinouts
SN74SSQEA32882 pinout,Pin out
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