1.5V/1.8V 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST

This 25-bit 1:1 or 14-bit 1:2 configurable registered Buffer is designed for 1.425-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads. All inputs are SSTL_18, except the reset ( RESET ) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meets SSTL_18 and SSTL_15 specifications (depending on Supply voltage level), except the open-drain error ( QERR ) output. The SN74SSTEB32866 operates from a differential Clock (CLK and CLK ). Data are registered at the crossing of CLK going high and CLK going low. The SN74SSTEB32866 accepts a parity bit from the Memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D2 – D3, D5 – D6, D8 – D25 when C0 = 0 and C1 = 0; D2 – D3, D5 – D6, D8 – D14 when C0 = 0 and C1 = 1; or D1-D6, D8-D13 when C0 = 1 and C1 = 1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is even parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs, combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be tied to a known Logic state. When used as a single device, the C0 and C1 inputs are tied low. In this configuration, parity is checked on the PAR_IN input signal, which arrives one cycle after the input data to which it applies. Two Clock cycles after the data are registered, the corresponding partial-parity-out (PPO) and QERR signals are generated. When used in pairs, the C0 input of the first Register is tied low, and the C0 input of the second Register is tied high. The C1 input of both Registers are tied high. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input signal of the first device. Two Clock cycles after the data are registered, the corresponding PPO and QERR signals are generated on the second device. The PPO output of the first Register is cascaded to the PAR_IN of the second SN74SSTEB32866. The QERR output of the first SN74SSTEB32866 is left floating, and the valid error information is latched on the QERR output of the second SN74SSTEB32866. By Texas Instruments
Part Manufacturer Description Datasheet Samples
SN74SSTEB32866ZWLR Texas Instruments 1.5V/1.8V 25-Bit Configurable Registered Buffer With Address-Parity Test 96-BGA -40 to 85
SN74SSTEB32866 's PackagesSN74SSTEB32866 's pdf datasheet
SN74SSTEB32866ZWLR




SN74SSTEB32866 Pinout, Pinouts
SN74SSTEB32866 pinout,Pin out
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