25-Bit Configurable Registered Buffer With SSTL_18 Inputs And Outputs

This 25-bit 1:1 or 14-bit 1:2 configurable registered Buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.
The SN74SSTU32864 operates from a differential Clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low.
The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the Register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and should not be used.
The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, Clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all Registers are reset and all outputs are forced low. The LVCMOS RESET and Cn inputs always must be held at a valid Logic high or low level.
The two VREF pins (A3 and T3), are connected together internally by approximately 150 . However, it is necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin should be terminated with a VREF coupling capacitor.
The device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and will Gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the Qn outputs function normally. The RESET input has priority over the DCS and CSR control and forces the output low. If the DCS control functionality is not desired, the CSR input CAN be hard-wired to ground, in which case, the setup-time requirement for DCS is the same as for the other D data inputs.
To ensure defined outputs from the Register before a stable Clock has been supplied, RESET must be held in the low state during power up.
By Texas Instruments
Part Manufacturer Description Datasheet Samples
SN74SSTU32864EZKER Texas Instruments IC SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96, GREEN, PLASTIC, LFBGA-96, FF/Latch
SN74SSTU32864GKER Texas Instruments 25-Bit Configurable Registered Buffer with SSTL_18 Inputs and Outputs 96-LFBGA 0 to 70
SN74SSTU32864DGKER Texas Instruments 25-Bit Configurable Registered Buffer With SSTL_18 Inputs and Outputs 96-LFBGA 0 to 70
SN74SSTU32864ZKER Texas Instruments 25-Bit Configurable Registered Buffer with SSTL_18 Inputs and Outputs 96-LFBGA 0 to 70
SN74SSTU32864CGKER Texas Instruments SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96, PLASTIC, LFBGA-96
SN74SSTU32864CZKER Texas Instruments 25-bit configurable registered buffer with SSTL_18 inputs & outputs 96-LFBGA 0 to 70
SN74SSTU32864 's PackagesSN74SSTU32864 's pdf datasheet
SN74SSTU32864GKER LFBGA
SN74SSTU32864ZKER LFBGA




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SN74SSTU32864 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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