25-Bit Configurable Registered Buffer With Address-Parity Test

This 25-bit 1:1 or 14-bit 1:2 configurable registered Buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the reset (RESET)
By Texas Instruments
Part Manufacturer Description Datasheet Samples
SN74SSTU32866GKER Texas Instruments IC SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96, PLASTIC, LFBGA-96, FF/Latch
SN74SSTU32866 's PackagesSN74SSTU32866 's pdf datasheet
SN74SSTU32866GKER LFBGA
SN74SSTU32866ZKER LFBGA




SN74SSTU32866 Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
SN74SSTU32866 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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