25-Bit Configurable Registered Buffer With Address-Parity TestThis 25-bit 1:1 or 14-bit 1:2 configurable registered Buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the reset (RESET) By Texas Instruments |
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| Part | Manufacturer | Description | Datasheet | Samples | |
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| SN74SSTU32866GKER | Texas Instruments | IC SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96, PLASTIC, LFBGA-96, FF/Latch |
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| SN74SSTU32866 Pb-Free | SN74SSTU32866 Cross Reference | SN74SSTU32866 Schematic | SN74SSTU32866 Distributor |
| SN74SSTU32866 Application Notes | SN74SSTU32866 RoHS | SN74SSTU32866 Circuits | SN74SSTU32866 footprint |
