24-Bit To 48-Bit Registered Buffer With SSTL_2 Inputs And Outputs

This 24-bit to 48-bit registered Buffer is designed for 2.3-V to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.
The SN74SSTV32852 operates from a differential Clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, Clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all Registers are reset and all outputs are forced low. The LVCMOS RESET input always must be held at a valid Logic high or low level.
To ensure defined outputs from the Register before a stable Clock has been supplied, RESET must be held in the low state during power up.
By Texas Instruments
Part Manufacturer Description Datasheet Samples
SN74SSTV32852ZKFR Texas Instruments 24-Bit to 48-Bit Registered Buffer with SSTL_2 Inputs and Outputs 114-LFBGA 0 to 70
SN74SSTV32852GKFR Texas Instruments 24-Bit to 48-Bit Registered Buffer with SSTL_2 Inputs and Outputs 114-BGA MICROSTAR 0 to 70
SN74SSTV32852 's PackagesSN74SSTV32852 's pdf datasheet
SN74SSTV32852GKFR LFBGA
SN74SSTV32852ZKFR LFBGA




SN74SSTV32852 Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
SN74SSTV32852 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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